In this assignment, you will become familiar with how a basic 5-stage
pipeline works. You will be given a simulator that models an
unpipelined processor that implements a small MIPS-like instruction
set. Your assignment is to create a cycle-accurate simulator of a
pipelined version of this processor. Your simulator will perform data
forwarding, a simple branch prediction scheme, and the pipeline
interlocks to stall the pipeline when necessary. You will be using
accounts on the grace cluster. If you don't have one, go to the course
webpage and click on the link to get one. Project questions will be answered on the cs forum (http://forum.cs.umd.edu).