You will be simulating the MIPS ISA from Hennessy & Patterson, with some key differences. First, instead of a 64-bit architecture, you will implement a 32-bit architecture. In other words, all registers and data paths are 32 bits wide, and all instructions will operate on 32-bit operands. Second, to keep your simulator simple, you will only be required to support a scaled-down version of the MIPS ISA consisting of 11 instructions. These instructions, along with their encoding, are given in Table 1. We will adhere to the MIPS instruction formats presented in Figure B.27 of Hennessy & Patterson, with the exception that there is no ``shamt'' field in the R-type format, and instead the ``func'' field is 11-bits wide. Finally, although all immediate values in branch and jump instructions are left-shifted by 2, your BEQZ instruction SHOULD NOT perform the left shift.
Notice that all the instructions in Table 1 except for one exist in the normal MIPS ISA. These instructions behave exactly as described in the text (except they are 32-bit versions rather than 64-bit versions). The instruction we've added is ``HALT.'' As its name implies, when your simulator executes a HALT instruction, it should terminate the simulation. For more information about MIPS, consult the MIPs Language Section of appendix B of Hennessy & Patterson.