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| Class |
Chap |
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Comments |
| 1 |
One |
Intro, Survival Skills, Benchmarks |
Units and Amdahl's Law |
Start Ch. 1 HW, WS 1 |
| 2 |
|
Dreaded CPU Equation |
MIPS, MFLOPS and Machines |
|
| 3, 4 |
More Machine Details |
ISA and Assembly Language |
Start Appendix B ( WS 2) |
| 5,6,7 |
Appendix A |
Intro to MIPS ISA |
Intro MIPS Pipeline |
Start App A HW |
| 7,8 |
|
Pipeline Hazards: Data, Structural |
Control Hazards |
|
| 9,10 |
|
Multi-Cycle MIPS |
Loop Unrolling, Rescheduling |
WS 3W |
| 11 |
|
Control Hazards |
More Control Hazards |
|
| 12,13 |
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More Multi-Cycle DLX |
and More |
|
| 14, 15 |
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| 16,17 |
Three |
Scoreboard Algorithim |
Tomasulo Algorithm |
More Ch. 4 HW |
| 18,19 |
Five |
Other Instruction Level Parallelism |
Memory Hierarchy Basics |
Start Ch 5 HW, WS 5 |
| 20 |
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| 21,22 |
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Improving Memory Performance |
Main and Virtual Memory |
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| 23 |
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CPU and Memory CPI Effects |
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| 24 |
Seven, Eight |
Networks |
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Start Ch 7 HW--TBD |
| 25, 26 |
Six, Nine |
Multiprocessors Models |
Parallel Processor Models |
HW TBD |
| 27, 28 |
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Overview and Loose Ends |
Review |
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| 29 |
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Final Exam: TBA (check blackboard) |
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