DLX Load

(1) IR << Mem[PC]; NPC << PC +4

(2) A<< Regs[IR6..10]; B<<Regs[IR 11..15] ;

Imm << (IR16)16## IR 16..31

(3) ALUoutput << A+Imm

(4) LMD << Mem[ALUoutput]

(5) Regs[IR 11..15] << LMD

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