>>Use case 1
>>X and y are both volatile and initialized to 0.
>> Thread 1
>> x = 1
>> r1 = x
>> r2 = y
>> Thread 2
>> y = 1
>> r3 = y
>> r4 = x
>> Behavior in question: r1 = 1, r3 = 1, r2 = 0, r4 = 0
>from "Carr, Wayne" at "Mar 23, 2004 09:52:08 am"
>The behaviors you described are not legal.
That brings up an interesting point about observing a memory value in
store buffer without it being globally visible.
For IA64, the manual says:
Aligned st.rel and semaphore operations from multiple processors to
cacheable write-back memory become visible to all observers in a single
order (ie., in a particular interleaving; if it become visible to any
observer, then it is visible to all observers), except that for st.rel
each processor may observe (via ld or ld.acq) its own update prior to
it being observed globally.
On IA64, if x = 1 is a "st.rel [x]=1" and r1 = x is a "ld.acq r1=[x]"
without a "mf" in between then the load can see the value in its store
buffer without making it visible to other processors. The behavior
then becomes a possibility.
Are there other platforms that can observe a memory value in its store
buffer without having it become globally visible?
Regards.
Thomas Wang
Jeremy
-------------------------------
JavaMemoryModel mailing list - http://www.cs.umd.edu/~pugh/java/memoryModel
-------------------------------
JavaMemoryModel mailing list - http://www.cs.umd.edu/~pugh/java/memoryModel
This archive was generated by hypermail 2b29 : Thu Oct 13 2005 - 07:01:01 EDT