G'Day,
I apologize in advance because I'm surely simply missing and/or
misunderstanding something...
http://gee.cs.oswego.edu/dl/jmm/cookbook.html
"....
The ia64 cmpxchg instruction also has implicit barriers with
respect to the locations being loaded/stored, but additionally
takes an optional .acq (post-LoadLoad) or .rel (pre-StoreStore)
modifier. The form cmpxchg.acq can be used for MonitorEnter,
and cmpxchg.rel for MonitorExit. "
Could it be that cmpxchg.acq also results in "post"-LoadStore
and cmpxchg.rel also results in pre-LoadStore in addition to
post-LoadLoad (.acq) and pre-StoreStore (.rel) mentioned above?
"However, an ExitEnter (StoreLoad) barrier is in general still
needed between successive MonitorExits and MonitorEnters. "
Why is an extra StoreLoad barrier needed between successive
MonitorExits and MonitorEnters via cmpxchg.rel/acq? Would
someone please elaborate?
Well, I did noticed the following:
"ExitEnter is needed between (dynamically) successive
synchronized blocks or methods to properly deal with code in
which one thread does:
synchronized(x) { x.afield = 1; }
...
synchronized(x) { int i = x.afield; }
and another does:
synchronized(x) { x.afield = 2; }
...
synchronized(x) { int i = x.afield; }
ExitEnter is the same as StoreLoad unless atomic instructions
are used in MonitorExit and/or MonitorEnter and at least one
of these provide a barrier with at least the properties of
StoreLoad, in which case it is a no-op. "
But I don't quite understand what's the problem here. :-(
Now, with respect to PowerPC... The cookbook says that isync
is a LoadLoad barrier. I don't think so. To the best of my
knowledge, the isync instruction can be used to build a sort
of "PowerPC version" of IA64's cmpxchg.acq with post-LoadLoad
(and post-LoadStore? please see the question above), but on
its own (without some "branch instruction that depends on the
value returned by a preceding Load instruction" -- pls see the
Book-E), it can NOT be used as LoadLoad barrier. The Book-E
actually says: "The isync instruction may complete before
storage accesses associated with instructions preceding the
isync instruction have been performed."
What am I missing and/or misunderstanding here? TIA.
regards,
alexander.
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