Think of a hose. Water goes in one end and is supposed to come out the other, with no early exit. Even though the ALU instructions do nothing in the MEM stage, they have to occupy that stage for at least one clock cycle, even in the absence of stalls.
Similarly, Store instructions do nothing in the WB stage. However, they still occupy it because the next instruction in the pipe is forced to spend a similar clock cycle in the MEM stage right behind it. That is, unless the operation of the MEM stage is modified too, there's no point to ending some instructions earlier than others if no instruction can take advantage of the extra cycle.