Problem 2: Hands OFF the ISA questions

Briefly answer the following questions, explaining your answer for full credit, of course.

2.1

True or False: The ISA uniquely determines the specifications of the hardware on which it is to be executed.

Nope. Can run same ISA on different platforms.

2.2

Why is the encoding of the ISA so important in designing a computer architecture? That is, speculate as to why so much of chapter 2 is spent justifying the decisions made in designing MIPS.

See cheat sheet. The ISA influences both CPI and IC. That just might have an effect on the execution time.

2.3

Why is byte alignment an issue? That is, why might an ISA forbid one to load a word from a specific address?

Typically because the memory is only wired for aligned accesses. In simple terms, it costs more money (and time delays) to support more than the byte, halfword, word, and doubleword used in the MIPS64. As stated in chapter 2, words are at addresses which are 0 mod 4, while aligned doubleword addresses are 0 mod 8.

For example, in each pair of MIPS instructions below, the first instruction results in a byte alignment error, while the second doesn't. To see this, compute the effective address for each operation-that is, assuming you know what one is.

Also, why might allowing the first instruction below cause problems?

Again, time. You'd have to fetch two aligned words to get all the pieces of the misaligned word.

And, are there any load/store instructions that are immune from byte alignment errors in MIPS?

Hint: What size entities have addresses that are 0 mod 1 in a byte addressable memory?

LW  R2, 7(R0) 	; 7 is not 0 mod 4
LW  R4, 128(R0) ; 128 is 0 mod 4

DADDI R8, R0, #99 ; 
SD  R3, 17(R8) 	  ; 116 is not 0 mod 8
SD  R5, 29(R8) 	  ; 128 is still 0 mod 8
                  ; not dest, source format (!)

DADDI R9, R0, #1050;
L.D  F2,-1 (R9) 	; 1049 is not 0 mod 8
L.D  F4,-26(R9) 	; 1024 is  0 mod 8
S.D  F11, 998(R9)       ; 2048 is 0 mod 8
                        ; Okay for MIPS 64
                        ; F11 is NOT a DP FPR pair for MIPS 32

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