Ins Type | #Ins(Freq) | CCt |
ALU | .44 | 1 |
Load | .21 | 2 |
Store | .12 | 2 |
Branch | .23 | 2 |
A proposed modification to the ISA would replace one fourth of the ALU instructions, that are paired with a loaded operand that is never used again, with a new ALU2 instruction that incorporates the previously loaded operand in the instruction word. While the addition of this ALU2 instruction decreases the number of load instructions, the number of clock cycles for a branch is increased to three. The ALU2 instruction takes one clock cycle. So, the designers plan to use an optimizing compiler that will discard a third of the remaining ALU instructions.
Will this modified protocol improve the average execution time? Justify your answer using a quantitative approach, with the following table, to help you.
Ins Type | #(Not Freq) | CCt |
ALU | .22 | 1 |
ALU2 | .11 | 1 |
Load | .10 | 2 |
Store | .12 | 2 |
Branch | .23 | 3 |
Incorrect Answer:
Let CCT be the clock cycle time. Assume that it remains the same after the modification. Let IC be the instruction counts of the original system.
Speedup =
Note: This answer is numerically correct, but textually incorrect. Why? What's wrong with it.1
Answer: No, it is possible that their performance is not the same.
Answer: Evaluate the effect of the modification quantitatively.
Let CCT be the clock cycle time. Assume that it remains the same after
the modification. Let ,
,
and
be the instruction counts of the STORE, ALU, LOAD and BRANCH
operations in the original system.
Speed up
=
=
MM Hugue 2018-09-06