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Performance Modeling for Fast IP Lookups
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Authors
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Girija Narlikar
Francis Zane
Bell Laboratories, Lucent Technologies
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Abstract
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In this paper, we examine algorithms and data structures for the
longest prefix match operation required for routing IP packets.
Previous work, aimed at hardware implementations, has focused on
quantifying worst case lookup time and memory usage. With the advent
of fast programmable platforms, whether network processor or PC-based,
metrics which look instead at average case behavior and memory cache
performance become more important. To address this, we consider a
family of data structures capturing the important techniques used in
known fast IP lookup schemes. For these data structures, we construct
a model which, given an input trace, estimates cache miss rates and
predicts average case lookup performance. This model is validated
using traces with varying characteristics. Using the model, we then
choose the best data structure from this family for particular
hardware platforms and input traces; we find that the optimal data
structure differs in different settings. The model can also be used
to select the appropriate hardware configurations for future lookup
engines. The lookup performance of the selected data structures is
competitive with the fastest available software implementations.
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