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A Time-Stamping Algorithm for Efficient Performance
Estimation of Superscalar Processors
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Authors
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Gabriel Loh <gabriel.loh@yale.edu>
Department of Computer Science, Yale University
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Abstract
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The increasing complexity of modern superscalar microprocessors makes
the evaluation of new designs and techniques much more difficult. Fast
and accurate methods for simulating program execution on realistic and
hypothetical processor models are of great interest to many computer
architects and compiler writers. There are many existing techniques,
from profile based runtime estimation to complete cycle-level
simulations. Many researchers choose to sacrifice the speed of
profiling for the accuracy obtainable by cycle-level simulators. This
paper presents a technique that provides accurate performance
predictions, while avoiding the complexity associated with a complete
processor emulator. The approach augments a fast in-order simulator
with a time-stamping algorithm that provides a very good estimate of
program running time. This algorithm achieves an average accuracy that
is within 7.5% of a cycle-level out-of-order simulator in approximately
41% of the running time on the eight SPECInt95 integer benchmarks.
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