Material to be Covered in Exam 2

Exam 2 will cover the topics listed below along with material from Chapters 3 and 4 H&P covered in the last exam. The exam will also cover material in chapter 4.3 on branch prediction schemes.

 

Chapter 5

 

Section 5.2

 

  1. Associative, set associative, direct mapped caches
  2. Replacement policies
  3. Write through, write back
  4. Write buffer for write through cache
  5. Dirty bits
  6. Write allocate, no-write allocate

 

Section 5.3

 

  1. Cache misses - compulsory, capacity, conflict
  2. Approaches for reducing cache misses - block size, associativity,
  3. Victim caches, hardware prefetching, compiler controlled prefetching,
  4. Restructuring programs improve temporal or spatial locality

 

5.4 Reducing cache miss penalty

 

  1. Checking write buffer 
  2. Send critical word to CPU first, or at least restart CPU when data shows up
  3. Nonblocking caches 
  4. Second level caches

 

 

 

5.6 Main memory

 

  1. wider main memory
  2. interleaved memory
  3. independent memory banks (or parallel machines)
  4. avoiding memory bank conflicts

 

5.7 Virtual memory

  1. Address translation (as covered in class)
  2. Relationship between address space, page size, page table entry size, number of levels of page tables, etc.
  3. TLB
  4. Segments