This section is meant to answer some questions that one might have concerning the differences between the G4 processor and the G3 that are not directly handled in the main page. Please keep in mind that we have will discuss some differences, not all. The MPC74xx implementation of the AltiVec instruction set allows for a significant improvement in vector operations. The G4 implements all instruction defined by the AltiVec specification. The AltiVec instruction set is designed to improve the performance of vector-intensive code. AltiVec-targed code can speed up two and three dimensional graphic functions 3-5 times. The MPC74xx has improved memory subsystem bandwidth. As a result of the new implementation of AltiVec instrucion set, more functional units are used. Thus, there is a higher requirement in throughput. This is accomodated by the changes in the memory subsystem data busses. All memory subsystem data busses are now 128 bit wide as opposed to the 64 bit ones found in the G3. Furthermore certain queues have been enlarged to provide support for the increased functional units required by AltiVec. MPC74xx floating-point unit has been improved multiplication latency Single-precision multiplication operations have a latency of 3 clock cycles on the G3 and double precision multiplication operations takes 4 clock cycles. The latter is reduced in the G4 because of implementation of a full double precision Floating Point Unit. As a result multiplication in the G4 has a latency that is one less than that of the G3 (latency of 3). This improvement however did not cross over into the floating point divide which like the G3 still has a latency of 17 clock cycles for single precision and 31 clock cycles of double precision. MPC74xx has reduced opportunity for bottlenecks. The G3 processor has a 6 entry instruciton buffer and a 6 entry completetion queue. The G4 has the same set up except there are 8 entries available in the complete queue. What does this mean? The G4's extra entries reduces the amount of possible bottlenecks posed by the new execution units(i.e. -- AltiVec). For more information, see the G4 architecture whitepaper