MIPS R4000 Integer Pipeline

The MIPS R4000 architecture's use of superpipelining increases load and branch delays, and also the amount of forwarding required among the stages.

Load Delays:

If the result of a load is used in the next instruction, it causes a 2 cycle stall in the R4000 pipeline. This is due to the fact that the result of the load is not available to later instrucitons until the DS stage.

Instruction 1 2 3 4 5 6 7 8 9 10 11
LW R1,(R2) IF IS RF EX DF DS TC WB      
ADD R3,R4,R1   IF IS RF stall stall EX DF DS TC WB

Branch Delays:

Taken branches result in a 3 cycle stall, as condition evaluation and branch target computation occur in the EX stage.

Instruction 1 2 3 4 5 6 7 8 9
Branch IF IS RF EX DF DS TC WB  
Delay Slot   IF IS RF EX DF DS TC WB
Stall     stall stall stall stall stall stall stall
Stall       stall stall stall stall stall stall
Branch Target         IF IS RF EX DF

An untaken branch results in no stalls, it simply uses a one cycle delay slot.

Instruction 1 2 3 4 5 6 7 8 9
Branch IF IS RF EX DF DS TC WB  
Delay Slot   IF IS RF EX DF DS TC WB
Branch Instruction + 2     IF IS RF EX DF DS TC
Branch Instruction + 3       IF IS RF EX DF DS

Forwarding

When compared to the simple 5-Stage DLX, the R4000 requires many more levels of forwarding.

5-Stage DLX forwarding for ALU register-register instructions can occur from the EX/MEM or the MEM/WB registers. The following table shows the possible sources and destination of forwarding for the 5-Stage DLX Integer pipeline.

Pipeline Register Source Opcode of Source Instruction Pipeline Register Destination Opcode of Destination Instruciton Destination of Forwarded Result
EX/MEM Register-register ALU ID/EX All Top ALU Input
EX/MEM Register-register ALU ID/EX Register-register ALU Bottom ALU Input
MEM/WB Register-register ALU ID/EX All Top ALU Input
MEM/WB Register-register ALU ID/EX Register-register ALU Bottom ALU Input
EX/MEM ALU Immediate ID/EX All Top ALU Input
EX/MEM ALU Immediate ID/EX Register-register ALU Bottom ALU Input
MEM/WB ALU Immediate ID/EX All Top ALU Input
MEM/WB ALU Immediate ID/EX Register-register ALU Bottom ALU Input
MEM/WB Load ID/EX All Top ALU Input
MEM/WB Load ID/EX Register-register ALU Bottom ALU Input

* Note: 'All' corresponds to the following instruction types: Register-register ALU, ALU-Immediate, Load, Store, and Branch

The R4000 pipeline has four sources for ALU register-register operations: EX/DF, DF/DS, DS/TC, TC/WB. The following table shows the possible sources and destinations of forwarding for the R4000 Integer pipeline.

Pipeline Register Source Opcode of Source Instruction Pipeline Register Destination Opcode of Destination Instruciton Destination of Forwarded Result
EX/DF Register-register ALU RF/EX All Top ALU Input
EX/DF Register-register ALU RF/EX Register-register ALU Bottom ALU Input
DF/DS Register-register ALU RF/EX All Top ALU Input
DF/DS Register-register ALU RF/EX Register-register ALU Bottom ALU Input
DS/TC Register-register ALU RF/EX All Top ALU Input
DS/TC Register-register ALU RF/EX Register-register ALU Bottom ALU Input
TC/WB Register-register ALU RF/EX All Top ALU Input
TC/WB Register-register ALU RF/EX Register-register ALU Bottom ALU Input
EX/DF ALU Immediate RF/EX All Top ALU Input
EX/DF ALU Immediate RF/EX Register-register ALU Bottom ALU Input
DF/DS ALU Immediate RF/EX All Top ALU Input
DF/DS ALU Immediate RF/EX Register-register ALU Bottom ALU Input
DS/TC ALU Immediate RF/EX All Top ALU Input
DS/TC ALU Immediate RF/EX Register-register ALU Bottom ALU Input
TC/WB ALU Immediate RF/EX All Top ALU Input
TC/WB ALU Immediate RF/EX Register-register ALU Bottom ALU Input
DS/TC Load RF/EX All Top ALU Input
DS/TC Load RF/EX Register-register ALU Bottom ALU Input
TC/WB Load RF/EX All Top ALU Input
TC/WB Load RF/EX Register-register ALU Bottom ALU Input

* Note: 'All' corresponds to the following instruction types: Register-register ALU, ALU-Immediate, Load, Store, and Branch