1. In the paper, the authors define software synthesis as a two-phase process: a machine independent software construction phase and a machine dependent software implementation phase.What is the advantage of this division?

Sol:  Software synthesis is defined as a two phase process by the authors. This division helps to plug-in different target languages,middleware,real-time operating systems, and hardware device configurations. For example,in the component mapping phase, all that needs to be done is configuring the hardware and the OS through automatic generation of configuration files,make files,header files, and dependency files.Even in the code generation phase,  some basic issues such as hardware portability,software portability and temporal correctness can be handled efficiently due to this division.

2.What is a Complex Choice Petri net and what is a real time Petri net?

Sol: 
A Complex-Choice Petri Net is a 4-tuple(P,T,F,M) where
a) P is a finite set of places
b) T is a finite set of transitions
c) F: (P X T) U (T X P) -> Y  is a weighted flow relation between places and transitions represented by arcs, where Y is the set of non-negative integers.
d) M: P -> N is the initial marking ( assignment of tokens to places)

For an example, look at the paper specified in the link below
http://portal.acm.org/citation.cfm?id=774789.774832

A real-time Petri Net is a 5-tuple(P,T,F,B,C) where
a) P is a finite set of places
b) T is a finite set of transitions
c) F: (P X T) U (T X P) -> Y  is a weighted flow relation between places and transitions represented by arcs, where Y is the set of non-negative integers.
d)B maps a transition 't' to its worst case execution time and deadline
e)C is the period for this petri net

For more details, refer to page 663 in VERTAF paper. Below is the link for that paper:
http://ieeexplore.ieee.org/search/wrapper.jsp?arnumber=1339277

3.How does VERTAF leverage UML models in testing embedded software? What extensions to the UML standard were needed to support VERTAF, if any?

Sol: VERTAF uses some classes of UML with minimal restrictions for automatic design and analysis. Out of all diagrams in UML, three diagrams were chosen for VERTAF , namely, class diagram,sequence diagram and statechart. They were chosen such that the information redundancy in user specification is minimized and at the same time adequate expressiveness in user specifications is preserved. A new relationship called 'deployment relationship' was introduced between a software class and a hardware class, which can be used to specify a hardware component onto which a software object is deployed. This is an essential feature in an embedded system.