IA-64 is a new instruction set architecture. It is not a newly designed RISC or CISC ISA, it is actually a new type of ISA. It strives to meet some of the real problems inherent today in the microprocessor market. There are two things that slow down computers significantly that IA-64 seeks to address: branch delays and memory latency.

IA-64 seeks to exploit instruction level parallelism to the highest degree. Intel and HP have called their method of exploiting this parallelism in IA-64 EPIC (Explicitly Parallel Instruction Computing). EPIC simulates parallelism by having the compiler find what instructions can be executed in parallel and "explicitly" package them for the CPU.

The compiler will create 128-bit packages that contain three instructions. Before the bundle of instructions there will be a template field that will tell the CPU which instructions in the bundle and the following bundle can be executed in parallel. This eliminates the need for the CPU to try and figure out which instructions are parallelizeable, the compiler will tell it explicitly in the template field.

The following illustration is courtesy of BYTE magazine, and shows more explicitly the IA-64 instruction format.

IA-64 takes a unique approach to reducing the consequences of branch delays. It uses what is commonly known as predication. The compiler can append a predicate to any instruction it chooses. The compiler will append predicates to instructions that depend on the outcome of a branch in order to help reduce branch penalties.

A predicate is a tag that allows a program to execute instructions on a conditional basis, the value of the predicate. The value of the predicate in turn depends on the outcome of a conditional statement.

The compiler assigns predicates to the instructions along both sides of a branch it finds. The CPU will execute instructions along both paths until the CPU has computed the proper branch path. The predicate of the proper path will be set to true, and the predicates of the wrong path will be set to false. The CPU can then write back the results of the instructions whose predicates were true, and discard the others.

The following illustration is courtesy of BYTE magazine, and explains predication pictorally.

Memory latency occurs because CPU processing speed is significantly faster than the speed of fetching data from memory. IA-64 suggests a new way to eliminate some memory latency problems, speculative loading.

Speculative loading can be understood very easily. The compiler tries to load data long before it is used so that when it is needed it is very close in fast memory. This includes loading data before the branch in which it occurs, known as hoisting. One of the aspects of IA-64 speculative loading that is vitally important is that if data is not able to be accessed early, IA-64 does not report an exception right away. It checks to see if the data is able to be accessed immediately before it is used, and if so does not report the exception. If it is still unavailable, then the exception is reported.

The following illustration is courtesy of BYTE magazine, and explains speculative loading.

Chips that use the IA-64 architecture will be different in two major ways. Firstly, they will have significantly more registers than current chips. IA-64 chips will have 128 integer-type GPR's and 128 FP registers, all programmer visible, random-access registers. IA-64 will also include 64 1-bit predicate registers for use with predication.

Secondly, the first IA-64 chips plan to be able to run software from old x86 and HP-UNIX machines. This ability requires the stripped down logic from these two old architectures to be integrated into the new IA-64 chip.

The design of IA-64 has allowed for it to be inherently scalable. Many parts of the design of IA-64 have contributed to this inherent ability, but the main contributor is the IA-64 instruction format. Additional execution units can be added to increase machine width without requiring a change in the ISA design.

This "Inherently Scalable" design will allow Intel to break into the market that is currently held by larger, faster machines. Intel hopes that by creating a chip that can be scaled up by chaining that they will be able to enter a processor market that has formerly been closed to them, mainframes.

Read on, and you will find out all that you ever wanted to know.