Checksumming: Cyclic Redundancy Check
based on r+1 bit pattern (generator) G known to tx and rx
treat data bits D as a binary number
obtain r-bit CRC R such that <D,R> divisible (modulo 2) by G
receiver divides <D,R> by G. non-zero remainder implies error
can detect all burst errors less than r+1 bits
widely used in practice (ATM, HDCL)