> If I understand your synopsis correctly, it will allow programmers to assume
> that r2=1, r5=0 is not allowed. However, this outcome is allowed since there
> is no inter-thread happens-before relationship here.
Thanks! I forgot that you can't condense it so far as to avoid
mentioning the fact that happens-before edges only occur when
volatile reads and writes are to same variable. I'll add this.
-Doug
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