CMSC 411 Computer Architecture
Superscalar Speculative Tomasulo
and Control Hazard
Quiz
Fall, 2002

Suppose that we have implemented a (0,3) GPR machine, using a Superscalar Speculative Tomasulo (SST) architecture that executes the MIPS ISA. For each of the questions in this section, write the letter T next to the statements below that are True, and briefly explain why the others are false.

1.1

The SST uses static scheduling to maximize the amount of ILP that can be exploited at execution time.

False: uses dynamic scheduling

1.2

An instruction will remain in the reorder buffer of the SST until all instructions issued during the same clock cycle have committed.

False: stays in reorder buffer until at the top and committed, or if speculated incorrectly, will be flushed.

1.3

The Ideal CPI of the SST is less than 1.

True: superscalar goal is CPI< 1

1.4

The SST compiler uses a branch delay slot to deal with control hazards.

False: branch delay slot is static handling of control hazards; speculative requires dynamic prediction.

1.5

Speculative execution permits the SST to issue several instructions in a single clock cycle.

False: superscalar permits several instructions to be issued in a single clock cycle. Speculative execution means that you predicted (prior to confirmation) the direction to be taken by a branch, and executed some instructions based on that speculation. At best, if you predicted correctly, you have no (or minimal) stalls because you kept executing along a correct path while the branch was being decided.

At worst, you have to flush all the incorrectly executed instructions, called ``speculated instructions'', and then execute the correct ones. however, the experienced branch penalty should still be no more than the time needed to evaluate the branch condition and start the correct next instruction (in the absence of memory delays, of course, but that's another issue)

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