CMSC 411 Computer Architecture
Superscalar Speculative Tomasulo
and Control Hazard
Quiz
Fall, 2002

Suppose that we have implemented a (0,3) GPR machine, using a Superscalar Speculative Tomasulo (SST) architecture that executes the MIPS ISA. For each of the questions in this section, write the letter T next to the statements below that are True, and briefly explain why the others are false.

The goal here is to make grading easy for me, not to trick you with bad wording. So, if you prefer, you may write E and explain your interpretation of the statement.

1.1

The SST uses static scheduling to maximize the amount of ILP that can be exploited at execution time

1.2

An instruction will remain in the reorder buffer of the SST until all instructions issued during the same clock cycle have committed.

1.3

The Ideal CPI of the SST is less than 1.

1.4

The SST compiler uses a branch delay slot to deal with control hazards.

1.5

Speculative execution permits the SST to issue several instructions in a single clock cycle.

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