Part 1: Short Answers, Please (20)

Briefly answer the following questions for 4 points each.

1. Explain the difference between Little-Endian and Big-Endian memory organizations; please feel free to use diagrams to make your explanation clear.

   Answer: If you don't think of the term ``memory address'' when you see the terms Big-Endian and Little-Endian, then you don't know your definition.

   Typically, we refer to memory as byte addressable. This means that aligned accesses occur at byte boundaries, and that byte, half-word, word, and double-word loads and stores must occur at predefined locations, as shown in the table below. Note that all data access instructions are considered to be integer instrcutions because they require the computation of the effective address using the INT ALU unit.

   Dest/Src	Memory	MIPS64	Effective
   Register	Access	OP Code	Address
   GPR (R0-R31)
   	load byte	LB	0 mod 1
   	store byte	SB	0 mod 1
   	load half word	LH	0 mod 2
   	store half word	SH	0 mod 2
   	load word	LW	0 mod 4
   	store word	SW	0 mod 4
   	load double word	LD	0 mod 8
   	store double word	SD	0 mod 8
   FPR (F0-F31)
   	load sp word	L.S	0 mod 4
   	store sp word	S.S	0 mod 4
   	load dp word	L.D	0 mod 8
   	store dp word	S.D	0 mod 8

   
   
   

   Just like books can be placed on a shelf on their sides, with their spines readable right side up or upside down (alternatly left to right or right left), or even their spines in, multi-byte words can be stored in memory with two specific byte orderings, as indicated by the location of the MSB, the most significant bit (often, the sign bit), and the location of the least significant bit (the LSB).

   While the table indicates how big each word or double word is, and the address at which any such entity resides, it doesn't tell you the byte address of the MSB (most significant bit) or the LSB (least significant bit). Typically, the LSB is the bit which is the coefficient of $2^{0}$, and the MSB is the bit which is the coefficient of $2^{31}$ (or $2^{63}$) when the word (or double word) is interpreted as an unsigned binary number. That is the focus of the Little-Endian or Big-Endian organization--how individual bytes of a multi-byte word are stored in memory. The MSB is the big end, and the LSB is the little end. The way to understand this is to remember the source of the name.

   Little Endian means, literally, little end, or LSB, in first.
   Big Endian means, literally, big end, or MSB,in first.

   So, in Little-Endian organization, the LSB is the byte at address 0 mod 4 of a word, and at address 0 mod 8 of a double word. The MSB is at address 3 mod 4 for a word, and at address 0 mod 7 of a double word.

   In Big-Endian organization, the MSB is the byte at address 0 mod 4 of a word, and at 0 mod 8 of a double word. For a word, the LSB is at an address which is 3 mod 4, word, and at address 7 mod 8 of a double word.

   Note that a big-endian byte-level organization says nothing about the bit-level organization. Some machines are byte-level big-endian, and bit-level big-endian. Others are byte-level big-endian, and bit-level little-endian. Both bit-flavors of little-endian machines exist as well, but, this is the last you will hear of bit-level ordering.

   For purposes of this course, we will always write the MSB on the left and the LSB on the right. Since MIPS assumes a Big Endian organization, the book will label the MSB as bit 0, and the LSB as bit 31 in a word, and is bit 63 in a double word.

2. Write a MIPS code fragment that will result in register R5 containing the value -262144 Hint: (262144 = $2^{18}$).

   Answer: There are lots of correct answers here. And, I will help you with arithmetic on exams too, in the absence of calculators.

   The fact that the number is greater than $2^{17}-1$, which is the base 10 equivalent of the unsigned binary number consisting of 16 ones, indicates that you can't possibly uses only one immediate (I-type) instruction to load this value without some major trickery (in case one of you can come up with a correct one-liner)

   Thus, any combination of two or more MIPS instructions with a post condition of R5 containing -262144 in 2's complement format is acceptable.

   Note that the 32-bit representations are:
   

   $$2^{18}\;\; = \;\; 0000 \;\;\; 0000\;\;\; 0000\;\;\; 0100\;\;\; 0000\;\;\; 0000\;\;\; 0000\;\;\; 0000_{2}$$
   
   
   
   
   $$-2^{18}\;\; = \;\;1111 \;\;\; 1111 \;\;\; 1111\;\;\; 1100\;\;\; 0000\;\;\; 0000 \;\;\; 0000\;\;\; 0000_{2}$$
   
   

   DADDUI	R5,	R0,	# 65535	;	That's 16 ones, or $2^{17}-1$
   DADDI	R5,	R5,	# 1	;	That's 1 and 16 zeros, or $2^{17}$
   DADD	R5,	R5,	R5	;	That's 1 and 17 zeros, or $2^{18}$
   DSUB	R5,	R0,	R5	;	R5 has $-2^{18}$

3. Write two different MIPS code fragments that will read a 64 bit number stored at address 128 in memory and place it in register R4.

   Answer: All you have to do is make sure that the effective address is 128. Three such possibilities are:

   Option 1:	LD	R4,		128(R0);
   Option 2:	DADD	R1,	R0,	R0;
   	LD	R4,		128(R1);
   Option 3:	DADDI	R1,	R0,	# 128;
   	LD	R4,		0(R1);

4. Recall that we have characterized general purpose register (GPR) machines as $(m,n)$ architectures, where MIPS is a (0,3) architecture. Under what conditions, if any, is the following instruction valid for a (0,3) GPR machine.

   S.D	F2, 24(R2);

   Answer: This is a nasty, annoying problem. The (0,3) GPR refers to the format of an ALU operation, not data moving operations. So, the GPR designation has nothing to do with the format of a store instruction. About the only possible assumption is that R2 is 0 mod 8, required to assure aligned access.

5. How would you characterize an architecture that supports the following command? You should assume that R2 is the destination register, and that R1 and R3 have already been initialized. As always, explain your answer for full credit.

   DADD	R2, (R1 + R3);

   Answer: Another sneaky, annoying problem. We have an ALU instruction that contains a memory reference, and has ony two operands. Thus, we know that this is probably a (1,2) architecture.

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