Multi-cycle datapath: instruction execution

Breaking instruction execution into multiple clock cycles:

Balance amount of work done in each cycle (minimizes the cycle time)

Each step contains at most one:

Register access

Memory access

ALU operation

Any data values which are needed in a later clock cycle are stored in a register

Major state elements: PC, register file, memory

Temporary registers written on every cycle: A data, B data, MDR,  ALUOut

Temporary registers with write control: IR

Note that we can read the current value of a destination register:

New value doesn't get written until next clock cycle

Multiple operations can occur in parallel during same clock cycle

Read instruction and increment PC

Other operations occur in series in separate clock cycles

Reading or writing standalone registers (PC, A data, B data, etc.) done in 1 cycle

Register file access requires additional cycle: more overhead for accessing