Multi-cycle datapath: control signals

New control signals

Fig. 5.32

IorD: selects PC (instruction) or ALUOut (data) for memory address

IRWrite: updates IR from memory (when?)

ALUSrcA: control to select PC or reg A (read data 1 from register file)

output is first operand for ALU

ALUSrcB: control to select second operand for ALU among 4 inputs:

0: reg B (read data 2 from register file)

1: constant 4

2: sign-extended immediate from instruction

3: above value shifted left by 2