Control unit: main

Main control signals

ALUOp: 2 bits based on op code used as input by ALU control

RegDst: selects from instruction bits 20-16 or 15-11 ($rt or $rd)

for destination register to write data

RegWrite: enables writing of destination register

ALUSrc: selects second input of ALU

0: Read data 2 from register file

1: sign-extended immediate from instruction

PCSrc: selects input to update PC

0: PC + 4 from adder

1: PC + offset from branch target calculation (other adder)

MemRead: data is read from data memory

MemWrite: data is written to data memory

MemtoReg: selects data to send to register file to write

0: ALU result

1: data read from memory

Can set all of these based only on opcode, except PCSrc

Should be set based on beq instruction AND ALU ouput is 0

Control unit generates Branch signal, which is ANDed with ALU Zero output