Complete implementation

MIPS-lite

arithmetic/logical: add, sub, and, or, slt

memory access: lw, sw

branch/jump: beq, j

Combine datapaths for

instruction fetch (Fig. 5.5)

R-type operations (Fig. 5.7)

Load and store (Fig. 5.9)

Branch (Fig. 5.10)

Jump (to be added)

Add control signals

Version 1: execute each instruction in 1 clock cycle

Version 2: execute each instruction in multiple (shorter) clock cycles