Register file: implementing | |||||||||||||||
Register file uses combinational logic with a set of registers | |||||||||||||||
We attach the outputs of each register to two buses, using tri-state buffers for each. | |||||||||||||||
|
|||||||||||||||
How to select the right registers? | |||||||||||||||
SRC 1 addr and SRC 2 addr | |||||||||||||||
How many bits for 4 registers? ceil( lg( 4 ) ) = 2 bits |