Problem 1: Memory Modeling

1.1

Briefly explain what is meant by the term Big Endian in the context of this course.

1.2

A 256K cache is implemented with a block-size of 4K bytes. Diagram the memory address, assuming that the organization of the cache is direct mapped. Be sure to label all parts of the 48-bit wide address correctly.

1.3

Suppose that the 256K cache described above is implemented using a slightly different organization strategy. How is the cache organized if the index is 5-bits long? Explain your answer for full credit.

1.4

Given a memory address, explain how to determine whether or not you have a read hit. Be specific regarding your use of the fields in the address and data areas of the memory.

1.5

A draft version of an architecture textbook claims that good memory organization can prevent at least 99% of all cache misses from occurring. Do you believe this statement, or do you think that there might be a typographical error on this page? Make sure you justify your answer clearly using the appropriate memory-related terminology.