Worksheet 3
Controlling Pipeline Hazards

Dr.  Michelle Hugue

This worksheet requires you to execute the MIPS code fragment on the next page using a variety of assumptions regarding the treatment of control hazards. The code is to be executed using the following modification of a Multicycle pipelined machine, similar to that presented in Appendix Section A.5 (?).

Functional Units:

There are separate computational pipes for integer and floating point ALU computations. Except for the otherwise indivisible divide, all floating point units are fully pipelined, meaning one stage per clock cycle. The floating point divide takes 30 clock cycles; the floating point adder/subtractor takes 5 clock cycles, and, the floating point multiply unit takes 10 clock cycles.

Registers:

Register writes occur in the first half of the clock cycle, and register reads occur in the 2nd half of the clock cycle.

Memory:

A Harvard Architecture is assumed, in which separate instruction and data memories are used. A perfect cache is assumed, and memory is assumed to be byte addressable.

Latencies:

Latencies and initiation intervals are as discussed in class, with INT ALU taking 1 clock cycle; latency between an ALU instruction producing a value and instruction using it is one less than the number of stages in the functional unit. Initiation interval is one for pipelined units, and the number of clockcycles for the divide.

Latency before a Store:

Remember, the latency in storing a value is one less than the latency associated with the functional unit producing the value, because the result is not need until the MEM stage.

Structural Hazards:

Should two ALU instructions complete their EX stages simultaneously and both require the MEM stage, the instruction that was started earlier gets the MEM stage, and the other instruction stalls in its last stage prior to the MEM stage.

RAW Hazards:

Assume that normal forwarding, bypassing, and load interlocks are implemented to minimize stalls due to RAW hazards. Stalls for RAW hazards occur after the ID stage, until the pipeline can proceed safely without any further delays to prevent this hazard.

WAW Hazards:

The 2nd instruction involved in a potential WAW hazard is stalled after the ID stage, waiting for the hazard to clear.

Control Hazards:

Each problem modifies the problem specification or design assmptions associated with the pipeline's treatment of branches. So, make sure that you indicate your assumptions clearly when doing your work to maximize your partial credit.

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