Part Two: Short Answers (18 points)

Briefly answer the following questions regarding the MIPS code fragment and the MMM-MIPS architecture. Be sure to explain your answers for full credit.

4.6

Are there any assumptions that must be made to assure that the code executes correctly? If so, give one. If not, then answer ``NONE''.

4.7

Could the offset corresponding to the label done in instruction (4) be stored at address V in instruction memory, where V is $3\; {\rm mod}\; 4$.

4.8

Could an exception occur while executing instruction (14)? If so, give an example of one. If not, explain why not.

4.9

Do you think that this code was generated by an optimizing compiler? Why or why not?

4.10

Would it be reasonable to modify the MMM-MIPS ISA to include two new branch types described below?

BLT	R1, R2, label	; Go to label if R1 $<$ R2.
BLE	R1, R2, label	; Go to label if R1 $\leq$ R2.

4.11

Based on this code fragment, do you believe that the MMM-MIPS uses a branch delay slot? Why or why not?

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