MMM-MIPS Specifications

The MMM-MIPS, Meesh's Maddening Magnificent-MIPS architecture, has an unquenchable thirst for MIPS, the ISA of choice for CMSC 311 and CMSC 411. The MMM-MIPS is similar to the Multi-Cycle MIPS machine discussed in class, with the same five stages, and the EX stage consisting of four separate sub-pipes for integer and floating point ALU execution.

You must assume that the MMM-MIPS implementation includes the following features. Be sure to write down any additional assumptions you make on this exam paper.

• Separate instruction and data memories are used.
• Register reads and writes are split across a single clock cycle.
• Forwarding, bypassing, short circuiting, and load interlocks are implemented.
• Branches are resolved in the ID stage.
• Execution functional units satisfy Table FU (below).
• Execution functional units are fully pipelined wherever possible. That is, each pipeline stage takes one clock cycle.

Unit		# of Clock Cycles
INT ALU		1
FP ADD		8
FP MULT		18
FP DIV		60

FU:

EX Stage Functional Unit Table

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